The present invention relates to a semiconductor memory device, and more particularly to a multi-bank memory structure.
There has been known a multi-bank memory structure in which a plurality of banks that operate independently are disposed within a chip, and those memories are interleaved. That is, the interleave system operates so that while a certain bank is accessed by latching a row address at a row address latch circuit relating thereto, another row address for a different bank is transmitted from a processor to a latch circuit relating thereto. The system can therefore sequentially access two banks without waiting for the completion of the access of a previous bank. Also, while a certain bank is being accessed, another bank can conduct pre-charging or refresh operation. Further, when an I/O bus line is commonly used between banks which are subjected to interleave operation to conduct pipe-line operation, data from different banks can be sequentially outputted.
At present, in order to realize high-speed operation of the semiconductor memory, such a multi-bank memory structure has been adopted.
Hereinafter, as the multi-bank memory structure, a two-bank structure including banks A and B as shown in FIG. 1 will be described. Referring to FIG. 1, the bank A comprises two plates P1 and P2 and each plates P1 and P2 comprise a plurality of memory cells in a matrix. For example, in the plate P1, there are a plurality of word lines connected to a row address decoder RD1, a plurality of column select lines 1 to 4 connected to a column address decoder CD1 and a plurality of pairs of bit lines D1 to D4, DB1 to DB4 as shown in FIG. 2. The bit lines D1 to D4 is complementary to the bit lines DB1 to DB4. For, example, when the bit line D1 is a high level (eg., logic 1), the bit line DB1 is a low level (eg., logic 0). Each memory cells is arranged at a position crossing a respective pair of bit lines and a respective word line. The bit lines D1 to D4 in the plate P1 are commonly connected to an I/O bus line T1 and the bit lines DB1 to DB4 are commonly connected to an I/O bus line N1. The bus line T1 is complimentary to the bus line N1. The structure of the plate 2 is the same to that of the plate 1. Pairs of bit lines in the plate P2 are connected to a pair of I/O bus lines T2 and N2 in common. On the other hand, the bank B has the same structure to the bank A. Pair of bit lines D10, DB10, D20, DB20 in a plate P3 are connected to a pair I/O bus line T1 and N1 in common. Pair of bit lines in a plate P4 are commonly connected to a pair I/O bus line T2 and N2. The I/O bus lines T1, N1, T2, N2 are connected to a write buffer (WBUF) and a data amplifier (DAMP) 109 to write or read data.
Next, the operation of this memory device will be explained. By responding to the respective word line, data stored at a memory cell (not shown) coupled to the bit lines D1 and DB1 in the bank A is transmitted to the bit lines D1 and DB1. Then, the column selection line 1 is activated (High level) to transfer data from the bit lines D1 and DB1 to the I/O bus lines T1 and N1, respectively, and the data are outputted to the data amplifier (DAMP) 109 through the bank B. In this situation, no data stored at a memory cell (not shown) coupled to the bit lines D10 and DB10 in the bank B is transmitted to the I/O bus lines T1 and N1. Conversely, when the data in the bank B is transmitted to the I/O bus lines T1 and N1 from the bit lines D10 and DB10, data in the bank A is not transmitted to the I/O buses T1 and N1.
FIG. 3A shows a layout around a connection portion between the bit lines D10, DB10 and the I/O bus lines T1, N1 in the plate P3. FIG. 3B shows a cross sectional view of the portion shown in FIG. 3A lined IIIA-IIIA'. Two I/O bus lines T1/N1 run in a parallel with each other and a vertical direction. The I/O bus line N1 is connected to a diffusion region K1 via contacts 208 and 209. The I/O bus line T1 is connected to a diffusion region K4 via conducts 211 and 212. Bit lines D10 and DB10 run in a parallel with each other in a horizontal direction. The bit line D10 has an extended portion under the I/O bus line T1 connected to a diffusion region K5 via contacts 216 and 217. The bit line DB10 has an extended portion under the I/O bus line N1 connected to a diffusion region k2 via contacts 213 and 214. A column selection line 206 runs in a horizontal direction between the bit lines D10 and DB10 at the top view. The column selection line 206 is connected to a tungsten layer 204 via a contact 215 and the tungsten layer 204 is coupled to a gate electrode 203 via a contact 210. The bit lines D10 and DB10 are formed from a silicide layer as a lower conductive layer. The I/O bus lines T1 and N1 and tungsten layer 204 are formed from a tungsten (W) layer as an intermediate conductive layer. The column section line 206 is formed from an aluminum layer as an upper conductive layer.
In this example, when a column selection signal is supplied with a selected column selection line 206, the signal is transmitted through the contact 215, the tungsten layer 204 and the contact 210 to the gate electrode 203. Upon that, the diffusion layers K1 and K2 are rendered conductive and the diffusion layers K4 and K5 are rendered conductive. As a result, data on the bit line D10 is outputted to I/O bus line T1 and data on the bit line DB10 is outputted to the I/O bus line N1.
In this situation, as shown in FIG. 4A, interlayer capacitance exist between adjacent layers, e.g. ,between the bit lines D10, DB10 and the I/O bus lines T1, N1. In details, as shown in FIG. 4A, there are a coupling capacitance C1 between the I/O bus line T1 and the bit line D10, a coupling capacitance C2 between the I/O bus line T1 and the bit line DB10, a coupling capacitance C3 between the I/O bus line N1 and the bit line D10, and a coupling capacitance C4 between the I/O bus line N1 and the bit line DB10. It is noted that the widths of the bit lines relating to the capacitance C1 and C4 is larger than that of the bit lines relating to the capacitance C2 and C3 because contacts are made on the capacitance C1 and C4 sides.
Then, for example, the column selection signal 1 in the bank A is activated in response to a column address strobe (CAS) signal so that data on the bit lines D1 and DB1 is transmitted to the I/O bus lines T1 and N1 and outputted to the data amplifier (DAMP) through the bank B. In this time, the bank B is accessed by a row address strobe (RAS) signal to pre-charge the bit lines D10 and DB10 to an intermediate potential VCC/2 from a supply potential VCC and ground potential GND respectively during the data outputing through the bank B.
Upon pre-charging the bit lines D10 and DB10, the voltage levels on the I/O bus lines T1 and N1 are influenced by coupling capacitors C1 to C4 based on the pre-charging of the bit lines D10 and DB10. Here, if the bit lines D10 and DB10 are equal in line width to each other and kept constant, one of those bit lines D10 and DB10 is pre-charged from VCC potential to VCC/2, and the other bit line is pre-charged from GND potential to VCC/2, as a result of which a change in interlayer capacitance is symmetrical, and the influence thereof is canceled. That is, C1-C2=0, and C3-C4=0 are satisfied. However, because the bit line D10 has the contacts 216 and 217 at a position below the I/O bus line T1 and the bit line DB10 has the contacts 213 and 214 at a position below the I/O bus line N1, the widths of the bit lines D10 and DB10 are not identical with each other, thereby, the coupling capacitance becomes C1&gt;C2, and C4&gt;C3. For that reason, a voltage change based on the difference of the capacities C1 to C4 becomes large at a side where the contact is provided, so that noise is produced at the I/O bus lines and adversely affects the data outputted from the bank A. When a capacitance of the entire I/O bus lines is C.sub.IO, and a total difference in capacitance which is caused by unbalance in interlayer capacitance between the I/O bus line and the bit line is C.sub.BIT, C.sub.BIT is then about 1% of C.sub.IO and the bit line is fluctuated 3.3V by pre-charging. As a result, a noises of about 33 mV occurs in the I/O bus line because the influence of that fluctuation, as shown in FIG. 4B. The noise produced on the I/O bus lines directly leads to the deterioration of operation margin such that a malfunction of the data amplifier (DAMP) occurs, thus preventing the semiconductor memory from functioning properly when being highly integrated.
On the other hand, Japanese Laid-Open Patent Application No. 62-60255 shows a semiconductor memory of one transistor type, having a word line, a bit line, and a column address line between the bit line and the word line so as to reduce the capacitance of the bit line and the word line. However, since No. 62-60255 only shows that the interlayer capacitance between the word line and bit line is merely reduced, there is no explanation about the unbalance of capacitance based on a difference in the size of the lines. Further, even though the noise on the bit line is reduce, when a noise on a bus line occurs, there is a problem that a voltage corresponding to data on the bus line varies because of the noise so that the DAMP 109 outputs a wrong data finally.
As described above, in the multi-bank structure semiconductor memory, in the case where the I/O bus lines are commonly used between the multi-banks to conduct pipeline operation, there is a case in which data output which is caused by a CAS signal for access to a certain bank overlaps with a pre-charge of the bit line which is caused by a RAS signal for access to a bank through which the data output passes. In this situation, in the case where the coupling capacitance of the bit line and the I/O bus line is unbalanced, noises occurs in the I/O bus line due to pre-charging of the bit line, thereby deteriorating the operation margin and causing inaccurate read operation.